SJ Semiconductor Corporation

About SJ Semiconductor Corporation

Shenghe Jingwei Semiconductor (Jiangyin) Co., Ltd., established in 2014, is a leading global enterprise in advanced wafer-level packaging and testing for integrated circuits. With a registered capital of 151 million USD, the company specializes in mid-stage silicon wafer manufacturing using an independent professional foundry model to serve global clients. It provides comprehensive advanced packaging services, including wafer-level packaging (WLP) and multi-chip integration, aiming to enhance performance in high-computing power, high-bandwidth, and low-power consumption through heterogeneous integration beyond Moore's Law.

Products & Services

Wafer Bumping:An advanced wafer-level packaging technology using materials like copper, tin, and gold through photolithography and micro-electroplating for various chip applications and packaging needs.

CP Test (Wafer Testing):A process using automated test equipment to probe wafer-level chips, measure circuit and functional characteristics, confirm processing yield, and screen out defective chips to improve quality.

Wafer-Level Chip Scale Packaging (WLCSP):Addresses the high demands of mobile devices for chip performance, size, power consumption, and cost by leveraging silicon wafer processing for compact, efficient packaging.

SmartPoser™ (3D SiP Innovation):An innovative 3D multi-chip integration packaging structure and platform technology with patents in China and the US, enabling high-density integration through vertical and planar interconnection, double-sided RDL, and flip-chip processes for modular and miniaturized chip solutions.

SmartPoser-HD Technology:A wafer-level system integration solution derived from SmartPoser™ for high-density, ultra-thin 3D integration, supporting applications in mobile computing, edge, and high-performance computing with cost-effective packaging.

SmartAiP Technology:A 5G millimeter-wave antenna chip integration solution derived from SmartPoser™, supporting ultra-wideband signal transmission (24GHz to 43GHz) for smartphones with low power, high gain, and ultra-thin integration, with potential for RF front-end module integration.

Specialties

Mid-stage Silicon Wafer Manufacturing Wafer-Level Packaging (WLP) 3D Multi-Chip Integration High-Density RDL Technology 5G Millimeter-Wave Antenna Integration Heterogeneous Integration for High-Performance Chips (GPU, CPU, AI)

Funding History

Debug: View Raw Funding Data

#	Type	Amount Fields	Date Fields	Investors
1	RT: New Financing Round T: - FT: New Financing Round	A: 700000000 MR: - FA: $700 million FAN: 700000000	D: 2024-12-31 FD: 2024-12-31	9 investors
2	RT: Series C+ T: - FT: Series C+	A: 340000000 MR: - FA: $340 million FAN: 340000000	D: 2023-04-04 FD: 2023-04-04	10 investors

New Financing Round Latest

2024-12-31

$700.0M

9 investors (Pro only)

Series C+ 2023-04-04

$340.0M

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Growth Metrics

+45%

Employee Growth

YoY

3.2x

Funding Growth

Last Round

12

Markets

Operating

10K+

Customers

Active

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Team & Leadership

No team data available

Team information is not yet available for this company

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